// ===== REFERENCES =====
// [1] duck.ac 用户 saffah_codex_6s_agg2，提交 #104557 <https://duck.ac/submission/104557>
// （154.627634 ms = 本题进入时的 T，Accepted）。
// 用途：**本文件的正文是该件正文的逐字节副本**（本地归档 problems/wc2017b2/ref2/rival_104557.cpp）。
// 该件相对其上一代 #103639 的**全部**正文改动（tools/fnmd5.py: SAME=2 DIFF=3，全文 diff
// 只落在 run_avx2 / run_scalar / solve 三处）只有两条：
// (a) 内层"掩码 + popcount"循环换成 **carry-save 位平面计数器**：每 16 个 256-bit 差向量
// （= 64 字）用 csa_add3（3:2 压缩器）折成 5 个 0/1 位平面（one/two/four/eight/sixteen，
// 权重 1/2/4/8/16）；每块只对 weight-16 平面做一次半字节 LUT popcount 并乘 16 累加，
// one/two/four/eight 四个低位平面**跨块累积**，查询结束时统一计数。非 64 字的余数仍走
// 原来的精确路径。
// 该件自己声明此思想的来源是 W. Mula, N. Kurz, D. Lemire,
// "Faster Population Counts Using AVX2 Instructions" <https://arxiv.org/abs/1611.07612>
// （CC BY 4.0）的 carry-save adder popcount 电路；本文件按原样保留该声明与许可说明。
// (b) 旋转构建循环里 4 条 intrinsic 32B 取数 → 内联汇编 ldu256、2 条 storeu → 对齐 store
// （该件自述与它自己的 #102854 同一思想）。
// [2] duck.ac 用户 saffah_cc_v41_260924，提交 #103639 <https://duck.ac/submission/103639>
// —— [1] 的直接基座（相位分裂旋转、512 个查询分组），也是本账号 #103697 的逐字复刻对象。
// [3] duck.ac 用户 saffah_cc_v41_agg1（本账号），提交 #103697 <https://duck.ac/submission/103697>
// = 进入本轮时本账号的 mine（164.378350 ms）；其正文与 [2] 逐字节相同（header 之外 0 字节差异）。
// [4] duck.ac 用户 saffah_dsh_v41_0919，提交 #84242 <https://duck.ac/submission/84242>
// —— ldu256 内联汇编 32 字节取数的写法（经 [2] 的引用链传入本文件）。
// ======================
// ===== 思路 =====
// 进入时实测（python3 tools/exact.py wc2017b2）：mine = 164.378350（#103697），
// T = 154.627634（[1]，今天 07:35 发），显示列 [1.005*T] thr = 155.401772。
// 但**一发新最好件即翻严支**（RULES §6c / BRIEF §2.18.588）⇒ 真实目标 = 0.99*T + 1us
// = **153.082 ms** ⇒ 真缺口 11.296 ms（6.87%）。
//
// 本发的定位 = §2.18.349「先算抄下来能到哪」：我方 #103697 与 [2] 正文逐字节相同、判题机实测
// 164.378350 vs 他自己 164.376273（复现差 +0.001%），所以复刻 [1] 的读数预期就是他的
// 154.628 ms ⇒ **-5.9%，但离 153.082 仍差 1.55 ms（1.0%）** ⇒ 抄不够，本发之后必须再叠一刀。
// 之所以先交这一发：它是"一个变量"（复刻对手当前榜首），且机理清晰、可预期；把 CSA 与后续刀
// 混在一发里会失去"哪一半在起作用"的信息。
//
// 机理（判题机侧的账，§2.18.788 条数账）：内层每 4 字
// 旧：[4 取数 + 3 ALU 建 z + 5 ALU 半字节 LUT + sad + add_epi64] = 15 uop/4 字
// 新：16 个 z（含 64 条取数）+ 15 次 csa_add3(5 uop) + 每块 1 次 csa_count(7)+slli+add
// = (64 + 48 + 75 + 9)/16 ≈ 12.4 uop/4 字 ⇒ 前端 4 uop/cycle 上 -17% uop。
// 判题机实测值未知（本发就是去取这个值）；本地 gcc15 只能做正确性与形状验证。
//
// 正确性闸门（本地，全部必须过）：driver + 本件在 .cache/wc2017b2_big_rand.bin /
// big_maxlen.bin 上的 chk 必须等于 3752654484591095461 / 3223221539191264348（与 [3] 一致），
// 且小数据与 brute.cpp 对拍一致。正文既然与 [1] 逐字节相同，闸门只是复核。
// ================
// wc2017b2: 2-plane (4 bitset array) encoding + query grouping by relative bit offset.
//
// win(a,b) (a=s1[i], b=s2[i+delta]) holds iff a == ((b-1) mod 3).
// Encode a char v by an injective 2-bit code:
// s1 side: e0 = (a>=1), e1 = (a>=2) (00->0, 10->1, 11->2)
// s2 side: f0 = (g!=0), f1 = (g>=2) with g=(b-1)mod3 (00->0, 10->1, 11->2)
// then win <=> (e0==f0) && (e1==f1) <=> ~((e0^f0)|(e1^f1)).
// Count over a window = l - popcount(diff), 4 arrays instead of 6.
// delta = y-x with |delta| < n; rho = |delta| & 63 selects a pre-rotated copy, so the
// two streams are bit-aligned. Queries are grouped by rho so that only one rotated copy
// is hot at a time (the working set then fits in L2 instead of streaming from L3).
#include <cstring>
#include <immintrin.h>
#define MAXN 300005
#define MAXW (((MAXN + 63) / 64 + 12 + 3) & ~3) /* multiple of 4 words = 32B rows */
static unsigned long long E0[MAXW + 2] __attribute__((aligned(64))), E1[MAXW + 2] __attribute__((aligned(64))), F0[MAXW + 2] __attribute__((aligned(64))), F1[MAXW + 2] __attribute__((aligned(64)));
// The 256 pre-rotated copies (4 x 64 x 4694 x 8 B = 9388 KB) are replaced by ONE two-array
// scratch: the query loop is group-outer and uses only one rotation per group, so the rotation
// is generated for that group immediately before its inner loop. 9388 KB -> 75 KB.
static unsigned long long R0[MAXW + 2] __attribute__((aligned(64))), R1[MAXW + 2] __attribute__((aligned(64)));
static int ORD[MAXN];
static __m256i FMASK[256] __attribute__((aligned(64)));
static __m256i LMASK[256] __attribute__((aligned(64)));
static unsigned long long RQ[MAXN];
static int GHEAD[520], GCUR[520];
static int g_nw;
static unsigned long long WMASK[65];
#define SOLVE_ARGS int n, int q, char *s1, char *s2, int *q_x, int *q_y, int *q_len, unsigned *ans
#pragma GCC push_options
#pragma GCC target("avx2,popcnt")
// judge's g++-9 with no -march lowers _mm256_loadu_* into vmovdqu+{vinserti128}/{vextracti128}
// (the AVX-256 split-load tax). This one asm instruction emits the real 32-byte load.
__attribute__((target("avx2"))) static inline __m256i ldu256(const void *p) {
__m256i r; __asm__("vmovdqu %1, %0" : "=x"(r) : "m"(*(const __m256i *)p)); return r; }
static const signed char LUTA[32] __attribute__((aligned(32))) =
{0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4, 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
static const signed char LOW4A[32] __attribute__((aligned(32))) =
{15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15};
#define VLUT (*((const __m256i *)LUTA))
#define VLOW4 (*((const __m256i *)LOW4A))
static inline unsigned pc_avx2_diff(const unsigned long long *A0, const unsigned long long *A1,
const unsigned long long *B0, const unsigned long long *B1,
int from, int to) {
unsigned acc = 0;
__m256i accv = _mm256_setzero_si256();
int w = from;
for (; w + 4 <= to; w += 4) {
__m256i z = _mm256_or_si256(
_mm256_xor_si256(ldu256(A0 + w),
ldu256(B0 + w)),
_mm256_xor_si256(ldu256(A1 + w),
ldu256(B1 + w)));
__m256i c8 = _mm256_add_epi8(
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
}
unsigned long long t[4];
_mm256_storeu_si256((__m256i *)t, accv);
acc = (unsigned)(t[0] + t[1] + t[2] + t[3]);
for (; w < to; w++)
acc += (unsigned)__builtin_popcountll((A0[w] ^ B0[w]) | (A1[w] ^ B1[w]));
return acc;
}
#pragma GCC pop_options
#pragma GCC push_options
#pragma GCC target("avx2,popcnt")
__attribute__((target("avx2"),always_inline)) static inline __m256i csa_diff(
const unsigned long long *a0,const unsigned long long *a1,
const unsigned long long *b0,const unsigned long long *b1,int k) {
return _mm256_or_si256(
_mm256_xor_si256(ldu256(a0+k),ldu256(b0+k)),
_mm256_xor_si256(ldu256(a1+k),ldu256(b1+k)));
}
__attribute__((target("avx2"),always_inline)) static inline void csa_add3(
__m256i &hi,__m256i &lo,__m256i a,__m256i b,__m256i c) {
__m256i u=_mm256_xor_si256(a,b);
hi=_mm256_or_si256(_mm256_and_si256(a,b),_mm256_and_si256(u,c));
lo=_mm256_xor_si256(u,c);
}
__attribute__((target("avx2"),always_inline)) static inline __m256i csa_count(__m256i x) {
__m256i v=_mm256_add_epi8(
_mm256_shuffle_epi8(VLUT,_mm256_and_si256(x,VLOW4)),
_mm256_shuffle_epi8(VLUT,_mm256_and_si256(_mm256_srli_epi16(x,4),VLOW4)));
return _mm256_sad_epu8(v,_mm256_setzero_si256());
}
static void run_avx2(int n, int q, int *q_x, int *q_y, int *q_len, unsigned *ans) {
(void)n;
for (int gi = 0; gi < 512; gi++) {
int g = (gi >> 2) & 63;
int ph = gi & 3; /* this sub-pass's phase class */
if (GHEAD[gi] == GHEAD[gi + 1]) continue;
const unsigned long long *S0, *S1;
if ((gi >> 2) < 64) { S0 = F0; S1 = F1; } else { S0 = E0; S1 = E1; }
int corr = 0; /* B pointer correction (words) */
if (g) { /* rotation, built AT THIS PHASE: dst[m] = src_rot[m + ph] */
unsigned long long sh = 64 - g;
corr = ph;
{ /* vectorised rotation: 4 words per step */
__m128i vg = _mm_cvtsi32_si128((long long)g), vsh = _mm_cvtsi32_si128((long long)sh);
int i = ph, lim = g_nw + 2;
for (; i + 4 <= lim; i += 4) {
__m256i a0 = ldu256(S0 + i);
__m256i b0 = ldu256(S0 + i + 1);
__m256i a1 = ldu256(S1 + i);
__m256i b1 = ldu256(S1 + i + 1);
_mm256_store_si256((__m256i *)(R0 + i - ph), _mm256_or_si256(_mm256_srl_epi64(a0, vg), _mm256_sll_epi64(b0, vsh)));
_mm256_store_si256((__m256i *)(R1 + i - ph), _mm256_or_si256(_mm256_srl_epi64(a1, vg), _mm256_sll_epi64(b1, vsh)));
}
for (; i <= g_nw + 1; i++) {
R0[i - ph] = (S0[i] >> g) | (S0[i + 1] << sh);
R1[i - ph] = (S1[i] >> g) | (S1[i + 1] << sh);
}
}
S0 = R0; S1 = R1;
}
for (int t = GHEAD[gi]; t < GHEAD[gi + 1]; t++) {
unsigned long long rq = RQ[t];
int k = ORD[t];
int x = (int)(rq & 0x1FFFFFu), y = (int)((rq >> 21) & 0x1FFFFFu), l = (int)(rq >> 42);
int delta = y - x;
int dpos = delta >= 0;
int dw = dpos ? (delta >> 6) : ((-delta) >> 6);
/* branchless: the query start is min(x,y) and the A side is (E0,E1) when
y>=x else (F0,F1). The 50/50 branch here mispredicts on half the queries. */
int s = dpos ? x : y;
const unsigned long long *AB = dpos ? E0 : F0, *AC = dpos ? E1 : F1;
int w0, wl, d, lo, hi;
const unsigned long long *A0, *A1, *B0, *B1;
w0 = s >> 6; wl = (s + l - 1) >> 6; d = wl - w0; lo = s & 63; hi = ((s + l - 1) & 63) + 1;
A0 = AB + w0; A1 = AC + w0; B0 = S0 + w0 + dw - corr; B1 = S1 + w0 + dw - corr;
int wA = w0 & ~3, wZ = wl & ~3;
int o = w0 - wA, oL = wl - wZ;
const unsigned long long *pA0 = A0 - o, *pA1 = A1 - o, *pB0 = B0 - o, *pB1 = B1 - o;
int bend = wZ - wA;
__m256i accv = _mm256_setzero_si256();
if (bend == 0) {
__m256i z = _mm256_or_si256(
_mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)pA0), ldu256(pB0)),
_mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)pA1), ldu256(pB1)));
z = _mm256_and_si256(z, _mm256_and_si256(FMASK[o * 64 + lo], LMASK[oL * 64 + hi - 1]));
__m256i c8 = _mm256_add_epi8(
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
} else {
{
__m256i z = _mm256_or_si256(
_mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)pA0), ldu256(pB0)),
_mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)pA1), ldu256(pB1)));
z = _mm256_and_si256(z, FMASK[o * 64 + lo]);
__m256i c8 = _mm256_add_epi8(
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
}
int b = 4;
__m256i one=_mm256_setzero_si256(),two=one,four=one,eight=one;
for (; b + 64 <= bend; b += 64) {
__m256i ta,tb,fa,fb,ea,eb,sixteen;
#define CD(K) csa_diff(pA0,pA1,pB0,pB1,b+(K))
csa_add3(ta,one,one,CD(0),CD(4));
csa_add3(tb,one,one,CD(8),CD(12));
csa_add3(fa,two,two,ta,tb);
csa_add3(ta,one,one,CD(16),CD(20));
csa_add3(tb,one,one,CD(24),CD(28));
csa_add3(fb,two,two,ta,tb);
csa_add3(ea,four,four,fa,fb);
csa_add3(ta,one,one,CD(32),CD(36));
csa_add3(tb,one,one,CD(40),CD(44));
csa_add3(fa,two,two,ta,tb);
csa_add3(ta,one,one,CD(48),CD(52));
csa_add3(tb,one,one,CD(56),CD(60));
csa_add3(fb,two,two,ta,tb);
csa_add3(eb,four,four,fa,fb);
csa_add3(sixteen,eight,eight,ea,eb);
accv=_mm256_add_epi64(accv,_mm256_slli_epi64(csa_count(sixteen),4));
#undef CD
}
if (b > 4) {
accv=_mm256_add_epi64(accv,csa_count(one));
accv=_mm256_add_epi64(accv,_mm256_slli_epi64(csa_count(two),1));
accv=_mm256_add_epi64(accv,_mm256_slli_epi64(csa_count(four),2));
accv=_mm256_add_epi64(accv,_mm256_slli_epi64(csa_count(eight),3));
}
for (; b < bend; b += 4) {
__m256i z = _mm256_or_si256(
_mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)(pA0 + b)), ldu256(pB0 + b)),
_mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)(pA1 + b)), ldu256(pB1 + b)));
__m256i c8 = _mm256_add_epi8(
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
}
{
__m256i z = _mm256_or_si256(
_mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)(pA0 + bend)), ldu256(pB0 + bend)),
_mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)(pA1 + bend)), ldu256(pB1 + bend)));
z = _mm256_and_si256(z, LMASK[oL * 64 + hi - 1]);
__m256i c8 = _mm256_add_epi8(
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
_mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
}
}
{ unsigned long long t[4]; _mm256_storeu_si256((__m256i *)t, accv);
ans[k] = (unsigned)l - (unsigned)(t[0] + t[1] + t[2] + t[3]); }
}
}
}
#pragma GCC pop_options
static void run_scalar(int n, int q, int *q_x, int *q_y, int *q_len, unsigned *ans) {
(void)n;
for (int gi = 0; gi < 512; gi++) {
int g = (gi >> 2) & 63;
int ph = gi & 3;
if (GHEAD[gi] == GHEAD[gi + 1]) continue;
const unsigned long long *S0, *S1;
if ((gi >> 2) < 64) { S0 = F0; S1 = F1; } else { S0 = E0; S1 = E1; }
int corr = 0;
if (g) { /* build THIS sub-pass's rotation in place */
unsigned long long sh = 64 - g;
corr = ph;
for (int i = ph; i <= g_nw + 1; i++) {
R0[i - ph] = (S0[i] >> g) | (S0[i + 1] << sh);
R1[i - ph] = (S1[i] >> g) | (S1[i + 1] << sh);
}
S0 = R0; S1 = R1;
}
for (int t = GHEAD[gi]; t < GHEAD[gi + 1]; t++) {
unsigned long long rq = RQ[t];
int k = ORD[t];
int x = (int)(rq & 0x1FFFFFu), y = (int)((rq >> 21) & 0x1FFFFFu), l = (int)(rq >> 42);
int delta = y - x;
int dpos = delta >= 0;
int dw = dpos ? (delta >> 6) : ((-delta) >> 6);
/* branchless: the query start is min(x,y) and the A side is (E0,E1) when
y>=x else (F0,F1). The 50/50 branch here mispredicts on half the queries. */
int s = dpos ? x : y;
const unsigned long long *AB = dpos ? E0 : F0, *AC = dpos ? E1 : F1;
int w0, wl, d, lo, hi;
const unsigned long long *A0, *A1, *B0, *B1;
w0 = s >> 6; wl = (s + l - 1) >> 6; d = wl - w0; lo = s & 63; hi = ((s + l - 1) & 63) + 1;
A0 = AB + w0; A1 = AC + w0; B0 = S0 + w0 + dw - corr; B1 = S1 + w0 + dw - corr;
unsigned dd = 0;
for (int w = 0; w <= d; w++) {
unsigned long long m = (A0[w] ^ B0[w]) | (A1[w] ^ B1[w]);
if (w == 0) m &= ~WMASK[lo];
if (w == d) m &= WMASK[hi];
dd += (unsigned)__builtin_popcountll(m);
}
ans[k] = (unsigned)l - dd;
}
}
}
__attribute__((target("avx2,popcnt"))) static void build_all(int n, const char *s1, const char *s2) {
int nw = (n + 63) >> 6;
for (int i = 0; i <= nw + 1; i++) { E0[i] = E1[i] = F0[i] = F1[i] = 0; }
{
/* Vectorised plane build. E0 = (a != '0'), E1 = (a == '2'),
F0 = (c != '1'), F1 = (c == '0') -- algebraically identical to the
branchy version, but with no data-dependent branches at all
(the scalar form mispredicts ~4x per 3 characters on random input). */
const __m256i Z0 = _mm256_set1_epi8('0'), Z1 = _mm256_set1_epi8('1'), Z2 = _mm256_set1_epi8('2');
int i = 0;
for (; i + 32 <= n; i += 32) {
int w = i >> 6, b = i & 63;
__m256i v1 = _mm256_loadu_si256((const __m256i *)(s1 + i));
__m256i v2 = _mm256_loadu_si256((const __m256i *)(s2 + i));
unsigned e0 = ~(unsigned)_mm256_movemask_epi8(_mm256_cmpeq_epi8(v1, Z0));
unsigned e1 = (unsigned)_mm256_movemask_epi8(_mm256_cmpeq_epi8(v1, Z2));
unsigned f0 = ~(unsigned)_mm256_movemask_epi8(_mm256_cmpeq_epi8(v2, Z1));
unsigned f1 = (unsigned)_mm256_movemask_epi8(_mm256_cmpeq_epi8(v2, Z0));
if (b == 0) { E0[w] = e0; E1[w] = e1; F0[w] = f0; F1[w] = f1; }
else { E0[w] |= (unsigned long long)e0 << 32; E1[w] |= (unsigned long long)e1 << 32;
F0[w] |= (unsigned long long)f0 << 32; F1[w] |= (unsigned long long)f1 << 32; }
}
for (; i < n; i++) {
int w = i >> 6, b = i & 63;
int a = s1[i] - '0', c = s2[i] - '0';
if (a >= 1) E0[w] |= 1ull << b;
if (a >= 2) E1[w] |= 1ull << b;
int g = (c + 2) % 3;
if (g != 0) F0[w] |= 1ull << b;
if (g >= 2) F1[w] |= 1ull << b;
}
}
g_nw = nw;
for (int i = 0; i < 64; i++) WMASK[i] = (1ull << i) - 1ull;
WMASK[64] = ~0ull;
for (int o = 0; o < 4; o++)
for (int lo = 0; lo < 64; lo++) {
unsigned long long *p = (unsigned long long *)&FMASK[o * 64 + lo];
for (int j = 0; j < 4; j++) p[j] = (j < o) ? 0ull : (j == o ? ~WMASK[lo] : ~0ull);
}
for (int o = 0; o < 4; o++)
for (int hh = 1; hh <= 64; hh++) {
unsigned long long *p = (unsigned long long *)&LMASK[o * 64 + hh - 1];
for (int j = 0; j < 4; j++) p[j] = (j < o) ? ~0ull : (j == o ? WMASK[hh] : 0ull);
}
}
static inline int have_avx2(void) {
unsigned a, b, c, d;
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(1), "c"(0));
int osxsave = (int)((c >> 27) & 1u), avx = (int)((c >> 28) & 1u);
if (!(osxsave && avx)) return 0;
unsigned lo, hi;
__asm__ volatile("xgetbv" : "=a"(lo), "=d"(hi) : "c"(0));
if ((lo & 6u) != 6u) return 0;
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(7), "c"(0));
return (int)((b >> 5) & 1u);
}
void solve(SOLVE_ARGS) {
build_all(n, s1, s2);
// group queries by the relative bit offset (sign aware), counting sort
for (int i = 0; i <= 512; i++) GHEAD[i] = 0;
for (int k = 0; k < q; k++) {
int d = q_y[k] - q_x[k];
int ad = (d >= 0 ? d : -d);
int g = ((d >= 0) ? 0 : 64) + (ad & 63);
GHEAD[g * 4 + ((ad >> 6) & 3) + 1]++;
}
for (int i = 0; i < 512; i++) GHEAD[i + 1] += GHEAD[i];
for (int i = 0; i < 512; i++) GCUR[i] = GHEAD[i];
for (int k = 0; k < q; k++) {
int x = q_x[k], y = q_y[k], l = q_len[k];
int d = y - x;
int ad = (d >= 0 ? d : -d);
int g = ((d >= 0) ? 0 : 64) + (ad & 63);
int p = GCUR[g * 4 + ((ad >> 6) & 3)]++;
ORD[p] = k;
RQ[p] = (unsigned long long)(unsigned)x | ((unsigned long long)(unsigned)y << 21)
| ((unsigned long long)(unsigned)l << 42);
}
#ifdef TESTSCALAR
run_scalar(n, q, q_x, q_y, q_len, ans);
#else
if (have_avx2()) run_avx2(n, q, q_x, q_y, q_len, ans);
else run_scalar(n, q, q_x, q_y, q_len, ans);
#endif
}
| Compilation | N/A | N/A | Compile OK | Score: N/A | 显示更多 |
| Testcase #1 | 171.44 us | 108 KB | Accepted | Score: 50 | 显示更多 |
| Testcase #2 | 154.607 ms | 8 MB + 864 KB | Accepted | Score: 50 | 显示更多 |