代码

// ===== REFERENCES =====
// [1] duck.ac 用户 saffah_codex_6s_agg2，提交 #105464 <https://duck.ac/submission/105464>
//     （144.061255 ms，本题当前榜首）。用途：**本文件正文逐字节复制自该件**（完备性证明见
//     「思路」节 (2)）。取自该件的内容：
//       (a) arena 六个位平面数组的行距 `AUXSTRIDE` = `((MAXW+2+16)+3)&~3`
//           （每个平面相对前一个多偏 16 字 = 128B，4704 → 4716 字；
//            4716 字 = 589.5 条 64B 线 ⇒ 相邻平面错开半条线）；
//       (b) arena 基址 = `(char*)base + 16384`（`AUXBYTES` 与 `FALLBACKAR` 同步）；
//       (c) 内层 16 条差向量取数的**循环移位版 m8**（该件头部自述 "our cyclic m8 input order"，
//           继承自它自己的 #105332）。
//     [1] 的前一代 #105388 与它只差 (a)(b) 两个常量（4→16 字、4096→16384B），
//     我们已对该前代做过完备性证明（17130 B 逐字节相同）。
//     [1] 头部第 3 行自述 "duck.ac user saffah_cc_v41_agg1, https://duck.ac/submission/105308:
//     inherited full accepted arena-based CSA source"，即 [1] 承认其基座取自本账号 #105308。
// [2] 本账号 saffah_cc_v41_agg1，提交 #105308 <https://duck.ac/submission/105308>
//     （145.005907 ms）—— [1] 的直接基座，由本队 `w2b_` 代理产出：#105080 + **单一基址 +
//     编译期平面位移**（热环 174 → 170 条，控制 4 mov + 4 add → 2 mov + 2 add）+ arena 分配。
// [3] 本账号 saffah_cc_v41_agg1，提交 #105080 <https://duck.ac/submission/105080>
//     （149.945710 ms）—— **16 条差向量取数的 m8 交错序**（把每块的 16 条 32B 取数摊到全部
//     8 条 cache line 上，把访存并行度拉满；纯顺序改动、零新增 uop）。它的一般化形式
//     `t = (16/m)*(n mod m) + (n div m)`（m|16，m=1 与 m=16 同为恒等）与判题机多臂定价见本队
//     `problems/wc2017b2/notes.md`。
// [4] duck.ac 用户 saffah_codex_6s_agg2，提交 #104982 <https://duck.ac/submission/104982>
//     （150.975314 ms）—— [3] 的直接基座（quarter_interleave + vpmaddubsw 16-bit 通道累加）。
// [5] duck.ac 用户 saffah_codex_6s_agg2，提交 #104557 <https://duck.ac/submission/104557>
//     （154.627634 ms）—— carry-save 位平面 popcount 的算法与主体代码来源（经 [4] 链条传入）。
//     该件的 carry-save popcount 思想它自己声明来自 W. Mula, N. Kurz, D. Lemire,
//     "Faster Population Counts Using AVX2 Instructions" <https://arxiv.org/abs/1611.07612>
//     （CC BY 4.0，仅参考思想、未复制其文字或代码）；本文件按原样保留该声明。
// [6] duck.ac 用户 saffah_cc_v41_260924，提交 #103639 <https://duck.ac/submission/103639>
//     —— [5] 的直接基座（512 个相位子组 + 只建本子组 1/4 的旋转）。
// [7] duck.ac 用户 saffah_dsh_v41_0919，提交 #84242 <https://duck.ac/submission/84242>
//     —— 内联汇编 32 字节取数（`vmovdqu %1, %0`）的写法来源（经 [6] 链条传入）。
// ======================
// ===== 思路 =====
// 本发 = **当前榜首 #105464 的逐字节复刻**（`work/w2a_rep3_sub.cpp`，本队 w2a_ 的完备性证明件，
//        它自己已发出一发实测 143.993268 ms = 与原件 144.061255 差 -0.047%，复现噪声内）
//        **+ 两处与数值路径无关的改动**：
//   A) **尾部子块也走 CSA 累加器**：`for (; b < bend; b += 4)` 那段精确尾部是 **18 条/4 字**
//      （≈ 主块 170/64 的 **1.65 倍**），而每个查询平均有 `bend mod 64 ∈ [0,63]` ⇒ 31.5 字走这条贵路。
//      改法：先按 **16 字一折**（4 个差向量 + 3 条 `csa_add3` 折进 a1/a2/a4/a8；进位用半加器
//      `c1=a4&t2; a4^=t2; c2=a8&c1; a8^=c1`；w16 进位 c2 用同款 `csa_count_bytes+vpmaddubsw` 通道），
//      只剩 ≤15 字走原来的 4 字尾路。**每块固定收益**类刀。
//   B) **arena 补成整 2 MiB + `madvise(MADV_HUGEPAGE)`**：原 arena 只有 `AUXBYTES ≈ 245 KB`，
//      **该尺寸无法被 2 MiB 大页承载**（THP 只覆盖整 2 MiB 的 VMA）⇒ 本队上一轮那条"THP 判负"的臂
//      其实是**结构性空操作**。本发改成 `posix_memalign(2<<20, 2<<20)` + madvise，于是 6 个位平面
//      （原先跨 60 个 4K 页、贴着 L1 DTLB 的 64 条上限）可以落在 **1 条大页**上。
//      ⚠ 平面间几何（`AUXSTRIDE = ((MAXW+2+16)+3)&~3` 与基址 `+16384`）**逐字保留** ⇒ 只动页粒度。
//
// 判据：
//   * **同二进制多臂 probe**（`work/w2b_pb5.cpp`/`pb6.cpp`，Q=1.2e5，Σl=6.006420654e9，2 rep）：
//     B 侧（2 MiB arena）**-0.47% / -0.89%**（对照臂地板 0.08%~0.32%）；A 侧（225 KB arena）≈ 0。
//   * ★ **本队规程：probe 会严重低估"每块固定收益"类刀**（实例：本队上一发"单一基址"刀
//     probe 只读 -0.58%，**正式提交兑现 -3.29%**，5.7×）⇒ A 的 probe 读数 **不能据此判负**，
//     按规程只由**正式提交**定价 ⇒ 本发就是那次定价。
//   * 与布局无关的硬证据：gcc 9.3 汇编上主块循环 170 条；A 只动尾部结构（尾部 18 条/4 字 → ≤15 字）。
//
// 正确性闸门（本地，全部已过）：
//   ① `driver.cpp` + 本件：`.cache/wc2017b2_big_rand.bin` / `big_maxlen.bin` 上
//      chk = 3752654484591095461 / 3223221539191264348（与 #105464/#105388/#105308 逐位相同）；
//   ② **`work/w2b_diff.cpp`：七份引擎（BASE / +A / +A' / +A+A'+B / rep2栈 / rep3栈）+ 暴力统计，
//      3000 组随机小数据（n≤300、q≤200、l 随机 ⇒ 穷举尾部所有长度）⇒ bad = 0**；
//   ③ probe 全部臂 ck 逐位相同。分配失败有静态回退（FALLBACKAR），不会解空指针。
// ================
#include <cstdlib>
#include <sys/mman.h>
#include <cstring>
#include <immintrin.h>

#define MAXN 300005
#define MAXW (((MAXN + 63) / 64 + 12 + 3) & ~3)   /* multiple of 4 words = 32B rows */

#define AUXSTRIDE (((MAXW + 2 + 16) + 3) & ~3)
static unsigned long long *E0, *E1, *F0, *F1, *R0, *R1;
static inline void bind_arena(void *base) {
  unsigned long long *b = (unsigned long long *)((char *)base + 16384);
  E0 = b + 0 * AUXSTRIDE; E1 = b + 1 * AUXSTRIDE;
  F0 = b + 2 * AUXSTRIDE; F1 = b + 3 * AUXSTRIDE;
  R0 = b + 4 * AUXSTRIDE; R1 = b + 5 * AUXSTRIDE;
}
#define AUXBYTES (6 * AUXSTRIDE * 8 + 16384)
static unsigned long long FALLBACKAR[6 * AUXSTRIDE + 2048];
static inline void *arena_alloc(int huge) {
  void *p = 0;
  size_t _sz = 2u << 20;
  if (posix_memalign(&p, 2u << 20, _sz) == 0 && p) {
    if (huge) madvise(p, _sz, MADV_HUGEPAGE);
    return p;
  }
  return (void *)FALLBACKAR;   /* allocation fallback: never dereference NULL */
}
// The 256 pre-rotated copies (4 x 64 x 4694 x 8 B = 9388 KB) are replaced by ONE two-array
// scratch: the query loop is group-outer and uses only one rotation per group, so the rotation
// is generated for that group immediately before its inner loop.  9388 KB -> 75 KB.
static int ORD[MAXN];
static __m256i FMASK[256] __attribute__((aligned(64)));
static __m256i LMASK[256] __attribute__((aligned(64)));
static unsigned long long RQ[MAXN];
static int GHEAD[520], GCUR[520];
static int g_nw;
static unsigned long long WMASK[65];

#define SOLVE_ARGS int n, int q, char *s1, char *s2, int *q_x, int *q_y, int *q_len, unsigned *ans

#pragma GCC push_options
#pragma GCC target("avx2,popcnt")

// judge's g++-9 with no -march lowers _mm256_loadu_* into vmovdqu+{vinserti128}/{vextracti128}
// (the AVX-256 split-load tax).  This one asm instruction emits the real 32-byte load.
__attribute__((target("avx2"))) static inline __m256i ldu256(const void *p) {
  __m256i r; __asm__("vmovdqu %1, %0" : "=x"(r) : "m"(*(const __m256i *)p)); return r; }

static const signed char LUTA[32] __attribute__((aligned(32))) =
  {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4, 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
static const signed char LOW4A[32] __attribute__((aligned(32))) =
  {15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15};
#define VLUT (*((const __m256i *)LUTA))
#define VLOW4 (*((const __m256i *)LOW4A))

static inline unsigned pc_avx2_diff(const unsigned long long *A0, const unsigned long long *A1,
                                    const unsigned long long *B0, const unsigned long long *B1,
                                    int from, int to) {
  unsigned acc = 0;
  __m256i accv = _mm256_setzero_si256();
  int w = from;
  for (; w + 4 <= to; w += 4) {
    __m256i z = _mm256_or_si256(
        _mm256_xor_si256(ldu256(A0 + w),
                         ldu256(B0 + w)),
        _mm256_xor_si256(ldu256(A1 + w),
                         ldu256(B1 + w)));
    __m256i c8 = _mm256_add_epi8(
        _mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
        _mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
    accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
  }
  unsigned long long t[4];
  _mm256_storeu_si256((__m256i *)t, accv);
  acc = (unsigned)(t[0] + t[1] + t[2] + t[3]);
  for (; w < to; w++)
    acc += (unsigned)__builtin_popcountll((A0[w] ^ B0[w]) | (A1[w] ^ B1[w]));
  return acc;
}
#pragma GCC pop_options

#pragma GCC push_options
#pragma GCC target("avx2,popcnt")

__attribute__((target("avx2"),always_inline)) static inline __m256i csa_diff1(
    const unsigned long long *a0, const unsigned long long *b0, int k) {
  __m256i r,t;
  __asm__("vmovdqu %2, %0\n\t"
          "vpxor   %3, %0, %0\n\t"
          "vmovdqu %4, %1\n\t"
          "vpxor   %5, %1, %1\n\t"
          "vpor    %1, %0, %0"
          : "=&x"(r),"=&x"(t)
          : "m"(*(const __m256i *)(a0+k)),"m"(*(const __m256i *)(b0+k)),
            "m"(*(const __m256i *)(a0+AUXSTRIDE+k)),"m"(*(const __m256i *)(b0+AUXSTRIDE+k)));
  return r;
}
__attribute__((target("avx2"),always_inline)) static inline void csa_add3(
    __m256i &hi,__m256i &lo,__m256i a,__m256i b,__m256i c) {
  __m256i u=_mm256_xor_si256(a,b);
  hi=_mm256_or_si256(_mm256_and_si256(a,b),_mm256_and_si256(u,c));
  lo=_mm256_xor_si256(u,c);
}
__attribute__((target("avx2"),always_inline)) static inline __m256i csa_count_bytes(__m256i x) {
  return _mm256_add_epi8(
    _mm256_shuffle_epi8(VLUT,_mm256_and_si256(x,VLOW4)),
    _mm256_shuffle_epi8(VLUT,_mm256_and_si256(_mm256_srli_epi16(x,4),VLOW4)));
}
__attribute__((target("avx2"),always_inline)) static inline __m256i csa_count(__m256i x) {
  return _mm256_sad_epu8(csa_count_bytes(x),_mm256_setzero_si256());
}

static void run_avx2(int n, int q, int *q_x, int *q_y, int *q_len, unsigned *ans) {
  (void)n;
  for (int gi = 0; gi < 512; gi++) {
    int g = (gi >> 2) & 63;
    int ph = gi & 3;                                  /* this sub-pass's phase class */
    if (GHEAD[gi] == GHEAD[gi + 1]) continue;
    const unsigned long long *S0, *S1;
    if ((gi >> 2) < 64) { S0 = F0; S1 = F1; } else { S0 = E0; S1 = E1; }
    int corr = 0;                                     /* B pointer correction (words) */
    if (g) {              /* rotation, built AT THIS PHASE: dst[m] = src_rot[m + ph] */
      unsigned long long sh = 64 - g;
      corr = ph;
      {                                                /* vectorised rotation: 4 words per step */
        __m128i vg = _mm_cvtsi32_si128((long long)g), vsh = _mm_cvtsi32_si128((long long)sh);
        int i = ph, lim = g_nw + 2;
        for (; i + 4 <= lim; i += 4) {
          __m256i a0 = ldu256(S0 + i);
          __m256i b0 = ldu256(S0 + i + 1);
          __m256i a1 = ldu256(S1 + i);
          __m256i b1 = ldu256(S1 + i + 1);
          _mm256_store_si256((__m256i *)(R0 + i - ph), _mm256_or_si256(_mm256_srl_epi64(a0, vg), _mm256_sll_epi64(b0, vsh)));
          _mm256_store_si256((__m256i *)(R1 + i - ph), _mm256_or_si256(_mm256_srl_epi64(a1, vg), _mm256_sll_epi64(b1, vsh)));
        }
        for (; i <= g_nw + 1; i++) {
          R0[i - ph] = (S0[i] >> g) | (S0[i + 1] << sh);
          R1[i - ph] = (S1[i] >> g) | (S1[i + 1] << sh);
        }
      }
      S0 = R0; S1 = R1;
    }
    for (int t = GHEAD[gi]; t < GHEAD[gi + 1]; t++) {
      unsigned long long rq = RQ[t];
      int k = ORD[t];
      int x = (int)(rq & 0x1FFFFFu), y = (int)((rq >> 21) & 0x1FFFFFu), l = (int)(rq >> 42);
      int delta = y - x;
      int dpos = delta >= 0;
      int dw = dpos ? (delta >> 6) : ((-delta) >> 6);
      /* branchless: the query start is min(x,y) and the A side is (E0,E1) when
         y>=x else (F0,F1).  The 50/50 branch here mispredicts on half the queries. */
      int s = dpos ? x : y;
      const unsigned long long *AB = dpos ? E0 : F0, *AC = dpos ? E1 : F1;
      int w0, wl, d, lo, hi;
      const unsigned long long *A0, *A1, *B0, *B1;
      w0 = s >> 6; wl = (s + l - 1) >> 6; d = wl - w0; lo = s & 63; hi = ((s + l - 1) & 63) + 1;
      A0 = AB + w0; A1 = A0 + AUXSTRIDE; B0 = S0 + w0 + dw - corr; B1 = B0 + AUXSTRIDE;
      int wA = w0 & ~3, wZ = wl & ~3;
      int o = w0 - wA, oL = wl - wZ;
      const unsigned long long *pA0 = A0 - o, *AA1 = A1 - o, *pB0 = B0 - o, *BB1 = B1 - o;
      int bend = wZ - wA;
      __m256i accv = _mm256_setzero_si256();
      if (bend == 0) {
        __m256i z = _mm256_or_si256(
            _mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)pA0), ldu256(pB0)),
            _mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)AA1), ldu256(BB1)));
        z = _mm256_and_si256(z, _mm256_and_si256(FMASK[o * 64 + lo], LMASK[oL * 64 + hi - 1]));
        __m256i c8 = _mm256_add_epi8(
            _mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
            _mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
        accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
      } else {
        {
          __m256i z = _mm256_or_si256(
              _mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)pA0), ldu256(pB0)),
              _mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)AA1), ldu256(BB1)));
          z = _mm256_and_si256(z, FMASK[o * 64 + lo]);
          __m256i c8 = _mm256_add_epi8(
              _mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
              _mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
          accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
        }
        int b = 4;
        __m256i z=_mm256_setzero_si256(), a1=z, a2=z, a4=z, a8=z, t0=z, t1=z, t2=z, t3=z, t4=z, t5=z, t6=z, t7=z, t8=z, t9=z, t10=z, t11=z, t12=z, t13=z, fl=z;
        __m256i high16=z;
        for (; b + 64 <= bend; b += 64) {
#define CD(K) csa_diff1(pA0,pB0,b+(K))
          csa_add3(t0,a1,a1,CD(16),CD(24));
          csa_add3(t1,a1,a1,CD(32),CD(40));
          csa_add3(t2,a2,a2,t0,t1);
          csa_add3(t3,a1,a1,CD(48),CD(56));
          csa_add3(t4,a1,a1,CD(0),CD(8));
          csa_add3(t5,a2,a2,t3,t4);
          csa_add3(t6,a4,a4,t2,t5);
          csa_add3(t7,a1,a1,CD(20),CD(28));
          csa_add3(t8,a1,a1,CD(36),CD(44));
          csa_add3(t9,a2,a2,t7,t8);
          csa_add3(t10,a1,a1,CD(52),CD(60));
          csa_add3(t11,a1,a1,CD(4),CD(12));
          csa_add3(t12,a2,a2,t10,t11);
          csa_add3(t13,a4,a4,t9,t12);
          csa_add3(fl,a8,a8,t6,t13);
          high16=_mm256_add_epi16(high16,
              _mm256_maddubs_epi16(csa_count_bytes(fl),_mm256_set1_epi8(1)));
#undef CD
        }
        for (; b + 16 <= bend; b += 16) {
#define CDT(K) csa_diff1(pA0,pB0,b+(K))
          csa_add3(t0,a1,a1,CDT(0),CDT(4));
          csa_add3(t1,a1,a1,CDT(8),CDT(12));
          csa_add3(t2,a2,a2,t0,t1);
          { __m256i c1=_mm256_and_si256(a4,t2);
            a4=_mm256_xor_si256(a4,t2);
            __m256i c2=_mm256_and_si256(a8,c1);
            a8=_mm256_xor_si256(a8,c1);
            high16=_mm256_add_epi16(high16,
                _mm256_maddubs_epi16(csa_count_bytes(c2),_mm256_set1_epi8(1))); }
#undef CDT
        }
        if (b > 4) {
          __m256i hs=_mm256_madd_epi16(high16,_mm256_set1_epi16(1));
          __m256i h64=_mm256_add_epi64(_mm256_and_si256(hs,_mm256_set1_epi64x(0xffffffffULL)),
                                      _mm256_srli_epi64(hs,32));
          accv=_mm256_add_epi64(accv,_mm256_slli_epi64(h64,4));
          accv=_mm256_add_epi64(accv,csa_count(a1));
          accv=_mm256_add_epi64(accv,_mm256_slli_epi64(csa_count(a2),1));
          accv=_mm256_add_epi64(accv,_mm256_slli_epi64(csa_count(a4),2));
          accv=_mm256_add_epi64(accv,_mm256_slli_epi64(csa_count(a8),3));
        }
        for (; b < bend; b += 4) {
          __m256i z = csa_diff1(pA0,pB0,b);
          __m256i c8 = _mm256_add_epi8(
              _mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
              _mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
          accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
        }
        {
          __m256i z = _mm256_or_si256(
              _mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)(pA0 + bend)), ldu256(pB0 + bend)),
              _mm256_xor_si256(_mm256_load_si256((const __m256i *)(const void *)(AA1 + bend)), ldu256(BB1 + bend)));
          z = _mm256_and_si256(z, LMASK[oL * 64 + hi - 1]);
          __m256i c8 = _mm256_add_epi8(
              _mm256_shuffle_epi8(VLUT, _mm256_and_si256(z, VLOW4)),
              _mm256_shuffle_epi8(VLUT, _mm256_and_si256(_mm256_srli_epi16(z, 4), VLOW4)));
          accv = _mm256_add_epi64(accv, _mm256_sad_epu8(c8, _mm256_setzero_si256()));
        }
      }
      { unsigned long long t[4]; _mm256_storeu_si256((__m256i *)t, accv);
        ans[k] = (unsigned)l - (unsigned)(t[0] + t[1] + t[2] + t[3]); }
    }
  }
}

#pragma GCC pop_options

static void run_scalar(int n, int q, int *q_x, int *q_y, int *q_len, unsigned *ans) {
  (void)n;
  for (int gi = 0; gi < 512; gi++) {
    int g = (gi >> 2) & 63;
    int ph = gi & 3;
    if (GHEAD[gi] == GHEAD[gi + 1]) continue;
    const unsigned long long *S0, *S1;
    if ((gi >> 2) < 64) { S0 = F0; S1 = F1; } else { S0 = E0; S1 = E1; }
    int corr = 0;
    if (g) {                                          /* build THIS sub-pass's rotation in place */
      unsigned long long sh = 64 - g;
      corr = ph;
      for (int i = ph; i <= g_nw + 1; i++) {
        R0[i - ph] = (S0[i] >> g) | (S0[i + 1] << sh);
        R1[i - ph] = (S1[i] >> g) | (S1[i + 1] << sh);
      }
      S0 = R0; S1 = R1;
    }
    for (int t = GHEAD[gi]; t < GHEAD[gi + 1]; t++) {
      unsigned long long rq = RQ[t];
      int k = ORD[t];
      int x = (int)(rq & 0x1FFFFFu), y = (int)((rq >> 21) & 0x1FFFFFu), l = (int)(rq >> 42);
      int delta = y - x;
      int dpos = delta >= 0;
      int dw = dpos ? (delta >> 6) : ((-delta) >> 6);
      /* branchless: the query start is min(x,y) and the A side is (E0,E1) when
         y>=x else (F0,F1).  The 50/50 branch here mispredicts on half the queries. */
      int s = dpos ? x : y;
      const unsigned long long *AB = dpos ? E0 : F0, *AC = dpos ? E1 : F1;
      int w0, wl, d, lo, hi;
      const unsigned long long *A0, *A1, *B0, *B1;
      w0 = s >> 6; wl = (s + l - 1) >> 6; d = wl - w0; lo = s & 63; hi = ((s + l - 1) & 63) + 1;
      A0 = AB + w0; A1 = A0 + AUXSTRIDE; B0 = S0 + w0 + dw - corr; B1 = B0 + AUXSTRIDE;
      unsigned dd = 0;
      for (int w = 0; w <= d; w++) {
        unsigned long long m = (A0[w] ^ B0[w]) | (A1[w] ^ B1[w]);
        if (w == 0) m &= ~WMASK[lo];
        if (w == d) m &= WMASK[hi];
        dd += (unsigned)__builtin_popcountll(m);
      }
      ans[k] = (unsigned)l - dd;
    }
  }
}

__attribute__((target("avx2,popcnt"))) static void build_all(int n, const char *s1, const char *s2) {
  int nw = (n + 63) >> 6;
  for (int i = 0; i <= nw + 1; i++) { E0[i] = E1[i] = F0[i] = F1[i] = 0; }
  {
    /* Vectorised plane build.  E0 = (a != '0'), E1 = (a == '2'),
       F0 = (c != '1'), F1 = (c == '0')   -- algebraically identical to the
       branchy version, but with no data-dependent branches at all
       (the scalar form mispredicts ~4x per 3 characters on random input). */
    const __m256i Z0 = _mm256_set1_epi8('0'), Z1 = _mm256_set1_epi8('1'), Z2 = _mm256_set1_epi8('2');
    int i = 0;
    for (; i + 32 <= n; i += 32) {
      int w = i >> 6, b = i & 63;
      __m256i v1 = _mm256_loadu_si256((const __m256i *)(s1 + i));
      __m256i v2 = _mm256_loadu_si256((const __m256i *)(s2 + i));
      unsigned e0 = ~(unsigned)_mm256_movemask_epi8(_mm256_cmpeq_epi8(v1, Z0));
      unsigned e1 = (unsigned)_mm256_movemask_epi8(_mm256_cmpeq_epi8(v1, Z2));
      unsigned f0 = ~(unsigned)_mm256_movemask_epi8(_mm256_cmpeq_epi8(v2, Z1));
      unsigned f1 = (unsigned)_mm256_movemask_epi8(_mm256_cmpeq_epi8(v2, Z0));
      if (b == 0) { E0[w] = e0; E1[w] = e1; F0[w] = f0; F1[w] = f1; }
      else { E0[w] |= (unsigned long long)e0 << 32; E1[w] |= (unsigned long long)e1 << 32;
             F0[w] |= (unsigned long long)f0 << 32; F1[w] |= (unsigned long long)f1 << 32; }
    }
    for (; i < n; i++) {
      int w = i >> 6, b = i & 63;
      int a = s1[i] - '0', c = s2[i] - '0';
      if (a >= 1) E0[w] |= 1ull << b;
      if (a >= 2) E1[w] |= 1ull << b;
      int g = (c + 2) % 3;
      if (g != 0) F0[w] |= 1ull << b;
      if (g >= 2) F1[w] |= 1ull << b;
    }
  }
  g_nw = nw;
  for (int i = 0; i < 64; i++) WMASK[i] = (1ull << i) - 1ull;
  WMASK[64] = ~0ull;
  for (int o = 0; o < 4; o++)
    for (int lo = 0; lo < 64; lo++) {
      unsigned long long *p = (unsigned long long *)&FMASK[o * 64 + lo];
      for (int j = 0; j < 4; j++) p[j] = (j < o) ? 0ull : (j == o ? ~WMASK[lo] : ~0ull);
    }
  for (int o = 0; o < 4; o++)
    for (int hh = 1; hh <= 64; hh++) {
      unsigned long long *p = (unsigned long long *)&LMASK[o * 64 + hh - 1];
      for (int j = 0; j < 4; j++) p[j] = (j < o) ? ~0ull : (j == o ? WMASK[hh] : 0ull);
    }
}

static inline int have_avx2(void) {
  unsigned a, b, c, d;
  __asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(1), "c"(0));
  int osxsave = (int)((c >> 27) & 1u), avx = (int)((c >> 28) & 1u);
  if (!(osxsave && avx)) return 0;
  unsigned lo, hi;
  __asm__ volatile("xgetbv" : "=a"(lo), "=d"(hi) : "c"(0));
  if ((lo & 6u) != 6u) return 0;
  __asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(7), "c"(0));
  return (int)((b >> 5) & 1u);
}

void solve(SOLVE_ARGS) {
  static void *ar = 0;
  if (!ar) { ar = arena_alloc(1); bind_arena(ar); }
  build_all(n, s1, s2);
  // group queries by the relative bit offset (sign aware), counting sort
  for (int i = 0; i <= 512; i++) GHEAD[i] = 0;
  for (int k = 0; k < q; k++) {
    int d = q_y[k] - q_x[k];
    int ad = (d >= 0 ? d : -d);
    int g = ((d >= 0) ? 0 : 64) + (ad & 63);
    GHEAD[g * 4 + ((ad >> 6) & 3) + 1]++;
  }
  for (int i = 0; i < 512; i++) GHEAD[i + 1] += GHEAD[i];
  for (int i = 0; i < 512; i++) GCUR[i] = GHEAD[i];
  for (int k = 0; k < q; k++) {
    int x = q_x[k], y = q_y[k], l = q_len[k];
    int d = y - x;
    int ad = (d >= 0 ? d : -d);
    int g = ((d >= 0) ? 0 : 64) + (ad & 63);
    int p = GCUR[g * 4 + ((ad >> 6) & 3)]++;
    ORD[p] = k;
    RQ[p] = (unsigned long long)(unsigned)x | ((unsigned long long)(unsigned)y << 21)
          | ((unsigned long long)(unsigned)l << 42);
  }

#ifdef TESTSCALAR
  run_scalar(n, q, q_x, q_y, q_len, ans);
#else
  if (have_avx2()) run_avx2(n, q, q_x, q_y, q_len, ans);
  else run_scalar(n, q, q_x, q_y, q_len, ans);
#endif
}

评测结果